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Future Blog Post

less than 1 minute read

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This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

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This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

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This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

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Instructor

Long-Haul Training, NUST, Chip Design Center, 2024

I conducted Hands-on Training/Grading for AQL-Tech Solutions with Dr. Muhammad Imran. The training was delivered through the platform of NUST Chip Design Center. The following is a non-exhaustive list of contents covered.

  1. RISC-V Assembly Langauge Application Design
  2. Multi-Cycle/Pipelined RISC-V Processor Design in SystemVerilog
  3. Processor Design Evaluation using RISCV-DV Environment.
  4. Implementation of Cache Simulator and Caches in SystemVerilog